Fast & Efficient Chip Communication Tech
High-Speed and Low-Power Asynchronous Network-on-Chip System Based Multiple-Valued Current-Mode Logic
Tags: Tohoku University, Japan, Transportation & Automotive, Electronics & Robotics
This innovation introduces a high-speed, low-power asynchronous Network-on-Chip system leveraging multiple-valued current-mode logic to mitigate intra-chip interconnection complexities and clock-skew issues in synchronous designs. By managing timing locally, this asynchronous approach enhances robustness, reduces power dissipation, and increases speed, despite the potential delay from handshaking communication steps. The proposed scheme's multiple-valued encoding significantly refines the communication protocol, while its current-mode circuits boost the system's driving capability for rapid intra- and inter-chip networking. This technology has broad applications in designing efficient communication Large Scale Integrations (LSIs), such as many-core LSIs and multi-module Networks-on-Chip (NoCs), fostering potential in high-speed and low-power digital systems development.
IP Type or Form Factor: Design; Process & Method
TRL: Not specified
Industry or Tech Area: Automobiles Autonomous; Semiconductors
